1. Field of the Invention
The present invention relates to an apparatus for preventing transferring noises of a digital signal which is generated and transferred in a digital signal processor such as a microcomputer.
2. Description of the Related Art
During the operation of a digital signal processor such as a microcomputer, switchings (ON/OFF) are continuously repeated in internal transistors. By the switchings of the transistors, potential fluctuations or noises are generated in a power source or a signal line. And hence, when the potential fluctuations or noises are generated at the time of receiving and giving the signals via buses by respective functional blocks in the microcomputer, it brings about a false signal recognition and there is the possibility of malfunction of the microcomputer.
FIG. 1 shows a schematic equivalent circuit diagram of a C-MOS inverter circuit as one example of a circuit which receives and gives a digital signal.
In FIG. 1, reference characters R1 and R2 designate parasitic resistances, L1 and L2 designate parasitic impedances, C designates a parasitic capacity against a power source, Trl designates a Pch (P channel) transistor, Tr2 designates an Nch (N channel) transistor, 1 designates a power line connected to a power potential Vcc and 2 designates a ground line connected to a ground potential Vss.
In such C-MOS inverter circuit, when its input signal changes to the ground potential Vss from the power potential Vcc, the Pch transistor Trl transits to an ON state from an OFF state, and the Nch transistor Tr2 transits to the OFF state from the ON state. Conversely, when the input signal changes to the power potential Vcc from the ground potential Vss, the Pch transistor Trl transits to the OFF state from the ON state, and the Nch transistor Tr2 transits to the ON state from the OFF state.
These operations are called a switching operation of the inverter.
When the input signal of the inverter is switched to the ground potential Vss from the power potential Vcc and an output signal of the same is switched to the power potential Vcc from the ground potential Vss, a through current I.sub.K and a discharge current I.sub.J against load capacity flow. At this time, the power potential Vcc drops temporarily due to the resistance and inductance component which are parasitic on the circuit.
In FIG. 1, directions of arrows respectively indicate the flowing directions of electric currents I.sub.K and I.sub.j.
Conversely, when the input signal of the inverter is switched to the power potential Vcc from the ground potential Vss, and the output signal of the same is switched to the ground potential Vss from the power potential Vcc, the through current I.sub.K and a discharge current I.sub.H against the load capacity flow. At this time, the ground potential Vss rises conversely due to the same reason mentioned above.
A rate of such drop of the power potential Vcc and rise of the ground potential Vss varies with the number of switching transistors or the positional relationship between the switching transistor and the power line.
A wave-form diagram of FIG. 2 shows the signal potential fluctuation on the power line according to the inverter switchings. In FIG. 2, reference character h1 designates an output signal wave form of the inverter, h2 designates a wave form of the power potential Vcc and h3 designates a wave form of the ground potential Vss.
When the wave form hi of the inverter output signal changes to the power potential Vcc from the ground potential Vss, the wave form h2 of the power potential Vcc drops relatively largely, and the wave form h3 of the ground potential Vss rises slightly. When the wave form h1 of the inverter output signal changes to the ground potential Vss from the power potential Vcc, the wave form h2 of the power potential Vcc drops slightly and the wave form h3 of the ground potential Vss rises relatively largely.
Meanwhile, FIG. 3(a) shows a schematic view of signal lines wired closely on the bus, and FIG. 3(b) shows their equivalent circuit diagram.
In the figures, reference characters LD and LD' designates the signal lines wired closely, C1 and C2 designate parasitic capacities against the ground potential Vss, and C3 designates the parasitic capacity between the signal lines LD and LD'.
When the signal lines are wired closely on the bus as such, it is well known that the signal change in one signal line may be transferred to the signal of the other signal line by a capacity coupling due to the parasitic capacity C3 between the signal lines.
A wave-form diagram of FIG. 4 shows a state of change of a signal wave form h5 on the other signal line LD according to the change of a signal wave form h4 on one signal line LD'.
FIG. 5 is a circuit diagram showing an example of configuration, wherein two aforementioned inverter circuits (INV1, INV3) shown in FIG. 1 are used to constitute a signal output block 6 and a signal input block 10, and further, the two blocks are connected via a bus 7.
In FIG. 5, like reference characters in aforementioned FIG. 1 designate like or corresponding parts. A reference character INV4 designates an inverter circuit having the same configuration as the inverter circuit shown in FIG. 1 as same as INV1 and INV3, and disposed in the output block 6 or in the vicinity thereof. A current driving power of the inverter circuit INV4 is sufficiently large as compared with the other inverter circuits INV1, INV3, and is capable of driving the load capacity of about parasitic capacity of the bus 7.
In the following description, as to the signal on the signal line, the case where its potential is on the power potential Vcc side is referred to as data "1" or merely "1", and the case on the ground potential Vss side is referred to as data "0" or merely "0".
Hereupon, when the inverter circuit INV1 outputs "1" to the signal line LD on the bus 7 in the output block 6, and the output signal of the inverter circuit INV4 inverts to "1" from "0" when the inverter circuit INV3 receives the signal from the signal line LD in the input block 10, as shown in FIG. 2, the power potential Vcc of the output block 6 drops. A drop of the power potential Vcc is transferred to the signal line LD via the Pch transistor Trl of the inverter circuit INV1, and reaches an input terminal of the inverter circuit INV3 of the input block 10. Furthermore, when the drop amount of potential reaches a threshold level (usually one half of the power potential Vcc) of the inverter circuit INV3, it is transferred into the input block 10 as data "0" to cause malfunction of the input block 10.
When the inverter circuit INV1 outputs "0" to the signal line LD of the bus 7 in the case where the output signal of the inverter circuit INV4 inverts to "1" from "0", the above-mentioned same malfunction is produced.
When the signal line LD is disposed closely to the other signal line LD' also on the bus 7, since the capacity coupling is generated by the parasitic capacity between the lines, the signal change on the signal line LD' changes a potential of the signal line LD temporarily. Even in this case, when a noise level generated in the signal line LD reaches the threshold value of the inverter circuit INV3 in the input block 10, the input block 10 operates falsely.
As mentioned above, in the digital signal processor such as the microcomputer and the like, there was the possibility that the potential changes temporarily due to the potential fluctuations in the signal line which is to maintain the power potential Vcc or the ground potential Vss during the operation, or the signal change of the other signal line disposed in the bus, and thereby producing the malfunction when the input side circuit inputs the potential change as data signals.
In recent years, in the digital signal processor such as the microcomputer and the like, the low voltage power potential is becoming popular. And hence, in such processor, an absolute potential difference between the power potential Vcc and the ground potential Vss is small, and easily influenced by the aforementioned potential fluctuations and the change of the other signal.
Due to such circumstances, the invention of, for example, Japanese Patent Application Laid-Open No. 3-24601 (1991) has been proposed. However, in this invention, when data which is to be transferred originally is "1 or (0)", data "0 (or 1") is transferred at the same time, and two data are stored once in a memory for comparison in the input side circuit into which the signals are inputted. In such configuration, a real time processing is impossible, and even when comparing directly without storing in the memory, since it is necessary to request to the signal output side to output the signal again when the false signal is inputted, the real time processing is also impossible.